A Strategy of Eliminating Silicon Dislocation in 55 NM Node Technology

Dislocations are crystalline defects that can significantly change the electrical properties of semiconductor materials. In this paper, the lattice dislocation formed during 55 nm node high voltage (55HV) process have been studied in detail. By adjusting the conditions of ion implantation and temperature of thermal process, we found that thermal stress is the key process that inducing the lattice dislocation defects. Moreover, the dislocation defects were eliminated by reducing temperature in thermal process of HV and medium voltage (MV) gate oxide process. The improvement of the process not only improves the yield of 55HV product from about 1 % to about 96%, but also brings new insights in eliminating similar defects in the future.