Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic

This work explores homo- and heterojunction tunnel field-effect transistor (TFET)-based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homojunction TFET-based NAND and NOR logic circuits, it has been observed that NAND consumes less power than the NOR gate since current drawn by PTFET in the pull-up network of the NOR gate is higher. The delay of the homojunction TFET-based NOR logic gate is lower than that of the NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double-gate heterojunction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Heterojunction TFET-based NAND with the pseudo-derived logic circuit shows a lower propagation delay of 103 times and a reduction in power consumption by 0.75 times compared to the heterojunction NAND logic circuit. Heterojunction TFET-based NOR with pseudo-derived logic has the reduction in power consumption of 103 times and lower propagation delay than the heterojunction NOR logic circuit.