<title>Reconfigurable hardware accelerator for embedded DSP</title>

Many DSP applications require dedicated hardware to achieve acceptable levels of performance. This is particularly true of real-time applications that have strict timeline requirements on processing throughput and latency. This paper outlines an FPGA-based reconfigurable processor architecture targeted to embedded DSP applications. The processor core consists of a high gate count FPGA multichip module (MCM) supplemented with four dedicated floating point multipliers. A dual port data memory provides a 480 Mbyte/sec channel to the processor and a 240 Mbyte/sec channel to the external interface. Coefficient memories are also included for static look-up table storage. A configuration bit stream loaded from non-volatile memory or an external source is used to program the FPGA.