Simulations of short-channel and overlap effects in amorphous silicon thin-film transistors

Through the use of two-dimensional computer simulations, we study short-channel and overlap effects in amorphous silicon thin-film transistors. As large-area fabrication techniques can lead to conductive source-drain overlaps being deposited on a portion of the upper passivation layer of inverted-gate thin-film transistors, it is important to understand how these overlaps affect performance. In saturation, charge accumulates under the drain overlap shortening the effective channel length. We contrast the performance of thin-film transistors with and without overlaps as a function of gate length.