Full-chip optical proximity correction using lithography simulation

The application of Optical Proximity Correction for improving uniformity of printed dimensions at sub-half-micron resolution in a 0.35 micron CMOS process is described. Results are presented in terms of measurements made on polysilicon gates, at different pitches, which are compared to the uncorrected case. The impact of photomask and stepper lens qualities on dimensional control are also considered. Results presented are at the demonstrator stage but strategy for implementation in production is discussed.