13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

The LPDDR product family originally sought to minimize power consumption. As the LPDDR5X is released with a 33% increase in maximum operating speed, low-power and high-speed operations have become essential [1]. Moreover, expanding virtual space (AR, XR) and the artificial intelligence industry have accelerated demand for high-speed and low-power mobile DRAM products. Therefore, guaranteeing higher IO speed has become a significant concern in designing DRAM. This paper proposes a WCK correction strategy, a voltage-offset-calibrated receiver, and IO for DRAM test to achieve high-speed operation. The WCK correction strategy improves the 3-sigma 4-phase skew distribution by 65%. The offset-calibrated receiver with a 1-tap decision-feedback equalizer (DFE) enhances the voltage offset by 59%. IO for DRAM test reduces the parasitic capacitance of the DQ pad by up to 39%. Using these techniques for high-speed operation, the LPDDR5X achieves operating speed up to 10.5Gb/s at $V_{DD2H}=1.05V$ and 10.0Gb/s at $V_{DD2H}=0.95V$.