Towards wafer-scale racetrack memory

Racetrack memory is a non-volatile data-storage concept in which chiral magnetic domain walls are shifted by electrical current along nanowires, offering high density and energy efficiency. This dissertation advances its integration on 300 mm wafers using CMOS-compatible processes. Reconfigurable magnetic inhibitors, formed by adjacent ferromagnetic nanostructures, are investigated as controllable domain-wall pinning sites. Experiments and micromagnetic simulations demonstrate their use for domain-wall filtering, trapping, logic, and leaky-integrate-and-fire neuronal behavior. Further, a sensitive magnetic tunnel junction sensing stack is developed and optimized for domain readout, including the synthetic antiferromagnet, tunnel barrier, and free layer. Finally, a wafer-scale integration scheme combining metallization, nanostructured MTJs, and racetracks is proposed and experimentally pursued.