Analog CMOS Multiplier Circuits: Design and Comparative Analysis

Multiplication is a key computational step in analog signal processing circuits used in various low-power applications such as pre-ADC sensor data processing, controllers for power management circuits, and analog neural networks. This paper compares two analog multiplication approaches: a Trans-linear Loop based design and a Linear MOSFET based design. The operating principles, voltage and current ranges, and design trade-offs of both circuits are analyzed. Implementations are carried out in the open-source SKY130nm CMOS process and verified through simulations. The trans-linear circuit consumes less than 21.53 µW, while the Linear-MOSFET based circuit consumes 39.78 µW. Guidelines for circuit optimization are provided, highlighting trade-offs in accuracy, power consumption, and area overhead. Impact of device mismatches in the multiplier circuits is evaluated using Monte Carlo simulations. Simulation results demonstrate the performance and limitations of each approach, providing a reference for the design of analog multipliers.