Compact Modeling and Mitigation of Parasitics in Crosspoint Accelerators of Neural Networks

In-memory computing (IMC) can accelerate data-intensive tasks, such as matrix-vector multiplication (MVM) or artificial neural networks (ANNs) inference, by means of the crosspoint memory array, allowing to reduce time and energy consumption. IMC accuracy, however, is affected by nonidealities, such as variability of the conductive weights or IR drop along wires due to parasitic resistances, whose impact steeply increases with the increase of array size. This work proposes a compact model to assess the impact of nonidealities for various circuital implementations, together with architectural schemes for their mitigation based on replicated arrays. The proposed mitigation techniques allow to restore the ANN accuracy from 72.7% to 94.9%, close to the software accuracy of 96.9%, in view of an increased area and energy consumption.