Solutions to selected exercises in Computer architecture : a quantitative approach

1 Fundamentals of Computer Design Introduction to the Chapter 1 Exercises Exercise 1.1 Exercise 1.2 Exercise 1.4 Exercise 1.5 Exercise 1.7 Exercise 1.8 Exercise 1.9 Exercise 1.11 Exercise 1.12 Exercise 1.13 Exercise 1.14 Exercise 1.15 2 Instruction Set Principles and Examples Introduction to the Chapter 2 Exercises Exercise 2.1 Exercise 2.2 Introduction to Exercises 2.6-2.9 Exercise 2.6 Exercise 2.9 Exercise 2.10 Exercise 2.12 3 Pipelining Introduction to the Chapter 3 Exercises Exercise 3.1 Exercise 3.2 Exercise 3.3 Exercise 3.7 Exercise 3.9 Exercise 3.10 Exercise 3.11 Exercise 3.14 4 Advanced Pipelining and Instruction-Level Parallelism Introduction to the Chapter 4 Exercises Exercise 4.1 Exercise 4.4 Exercise 4.8 Exercise 4.10 Exercise 4.14 The Classic Five-Stage DLX The DLX with Scoreboarding The Tomasulo DLX Exercise 4.17 Exercise 4.18 Exercise 4.20 5 Memory-Hierarchy Design Introduction to the Chapter 5 Exercises Exercise 5.1 Exercise 5.3 Exercise 5.4 Exercise 5.5 Exercise 5.6 Exercise 5.8 Exercise 5.10 Exercise 5.14 6 Storage Systems Introduction to the Chapter 6 Exercises About the Fallacy on Page 549 and Figures 6.43 and 6.2 Exercise 6.3 Exercise 6.5 Exercise 6.6 Exercise 6.10 Exercise 6.17 Exercise 6.19 7 Interconnection Networks Introduction to the Chapter 7 Exercises Exercise 7.1 Exercise 7.3 Exercise 7.5 Exercise 7.6 Exercise 7.9 Exercise 7.12 Exercise 7.13 8 Multiprocessors Introduction to the Chapter 8 Exercises Exercise 8.1 Exercise 8.5 Exercise 8.7 Exercise 8.9 Exercise 8.13 Exercise 8.23 A Computer Arithmetic Introduction to the Appendix A Exercises Exercise A.3 Exercise A.4 Exercise A.6 Exercise A.7 Exercise A.11 Exercise A.12 Exercise A.14 Exercise A.20 Exercise A.21 Exercise A.27 Exercise A.28 B Vector Processors Introduction to the Appendix B Exercises Convoys, Chimes, and Cycles Exercise B.2 Exercise B.3 Exercise B.4 Exercise B.5 Exercise B.6 Exercise B.7 Exercise B.8 Exercise B.10 Exercise B.11