DRAM Structure with Prioritized Memory Bank using Multi-VT Bit Cells Architecture

Increasing demand for bigger dynamic random-access memory (DRAM) capacitance, rises the power consumption of memory. Higher power consumption brings to chip heating, memory work uncertainty, IR drop on the chip, etc. Along with this, memory access time is also one of the important points in the chip working. For power saving propose, low-power cells are used like High threshold voltage (VT) standard cells. However mentioned cells have high transition time, which brings to memory access time increase. This paper represents Multi-Vt bit cell memory architecture, which is combined with the memory bank prioritizing algorithm, which is aimed to solve upper mentioned issues. Prioritizing of memory is based on counting each memory address access times and assigning unique cost number to them. Later this cost value is used to reconfigure memory addresses to have appropriate threshold voltage (VT) memory cell where the address is commonly used. The memory address mapper block is used for controlling memory block addressing. Testing results show, that using the proposed method of power consumption reduced by 5% compared with the standard Low VT memory bank. However, as control logic is used to switch between memory banks, the overall logical cell count is increased by 10%. Logic cell count increase brings an additional area increase in the design.