Process‐Driven Enhancement of Contact and Reliability Characteristics in Self‐Aligned Top‐Gate In–Ga–Zn–O Thin‐Film Transistors via Overetching and Ultrathin SiO 2 Interlayers

In this study, we present a process optimization strategy to improve the contact performance and bias stress reliability of self‐aligned amorphous In–Ga–Zn–O (IGZO) thin‐film transistors (TFTs) through systematic engineering of the source/drain (S/D) region. A top‐gate top‐contact (TGTC) IGZO TFT structure was fabricated, incorporating varied overetched margins (10%, 30%, and 50%) at the S/D and channel interface, as well as ultrathin SiO 2 interlayers (0, 2, and 8 atomic layer deposition (ALD) cycles) deposited at low temperature (100°C). The combined effect of oxygen vacancy modulation by overetching and shallow donor formation by hydrogen incorporation from ALD‐deposited SiO 2 layers enabled significant improvements in device performance. Notably, the configuration with a 30% overetched margin and 8‐cycle SiO 2 insertion achieved a high field‐effect mobility of 26.45 cm 2 /V s, a low contact resistance of 4211.7 Ω/μm, and excellent bias stability with a threshold voltage shift (Δ V TH ) of –0.109 V under positive bias stress ( V GS = +7 V, 3000 s). X‐ray photoelectron spectroscopy (XPS) confirmed the modulation of oxygen vacancy concentration and OH bond formation depending on the interlayer thickness. These results highlight the critical role of interface and process engineering in enhancing the electrical and reliability characteristics of oxide TFTs, providing a viable route for next‐generation high‐performance oxide‐based electronics.