Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers

Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for successfully subsequent processes. In this paper, a wafer-level warpage modeling methodology has been developed by the finite element analysis method using an equivalent material model. The developed modeling methodology has been verified by numerical results and experimental data. Using the developed model, wafer warpage has been simulated and analyzed by considering different factors, such as annealing temperature, copper (Cu) overburden thickness, TSV depth, and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and Cu overburden thickness. Such findings have been successfully used in TSV process optimization to reduce wafer warpage after annealing process. A global-local modeling methodology has also been implemented to determine wafer stress accurately. Wafer bending stress is high at wafer surface and close to TSV edge. Wafer bending stress increases with increasing TSV diameter and it is higher at the edge of TSVs with finer pitch.