材料科学
化学机械平面化
微观结构
泥浆
薄脆饼
无定形固体
复合材料
锡
透射电子显微镜
冶金
图层(电子)
光电子学
纳米技术
结晶学
化学
作者
Bingquan Wang,Yuhong Liu,Jie Cheng,Ruiheng Yan,Xinchun Lu
摘要
Through silicon via (TSV) technology is widely used to achieve 3D integration of integrated circuits. Chemical mechanical planarization (CMP) is a mature technology to achieve both local and global planarization which can be applied in the traditional 1st back side via reveal (BVR) process during the back side thinning and flattening of TSV wafers. In this paper, the surface and subsurface micro-damage of the TSV heterogeneous microstructure after back side CMP process was observed and characterized by cross-sectional transmission electron microscope (TEM) measurements, microscopic high resolution Raman spectra and I-V curves were also measured. As the results, CMP introduces micro-damage to surface and subsurface of Cu (local defects), of interface between Cu and barrier material (bimetallic corrosion), of Si (amorphous layers) and of insulation material (leakage current). The results illustrate that CMP induced amorphous Si layer shows barrier property, CMP changes the barrier property of Ti/TiN little, slurry formulation changes the insulation property of polished TEOS much, the addition of 5 mM BTA to CMP slurry and the controlling of pH≈10.5 can help to protect the back side surface of TSV wafers during CMP and to reduce the surface and subsurface damage of the back side metal structures. The conclusions in the research will guide the further research of TSV back side CMP and BVR process.
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