0.021-μm 2 High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery

This article introduces the industry’s first volume-production silicon-validated static random access memory (SRAM) designs fabricated using Intel’s 18A RibbonFET technology, incorporating PowerVia backside power delivery. The high-density 0.021- $\mu $ m² SRAM cell achieves an array density of up to 38.1 Mb/mm². With a high volume 34.3 Mb/mm² macro implementation in silicon demonstrating improved minimum operation voltage ( $V_{\mathrm {MIN}}$ ) with negative bitline (NBL) assist compared to similar designs on FinFET technology. Additionally, the high-current 6T SRAM high-current cell (HCC) exhibits improved $V_{\mathrm {MIN}}$ without the need for assist techniques, in contrast to equivalent FinFET implementations that require both read and write assist mechanisms. The HCC macro demonstrates a frequency up to 5.6 GHz when operating at 1.05 V.