Investigation of Threshold Voltage Instability of SiC MOSFETs Under Different Gate Voltage Sequences

The threshold voltage ( ${V}_{\text {th}}{)}$ instability of SiC MOSFETs is much more serious than that of Si MOSFETs. For most purposes, it is beneficial to perform an additional preconditioning prior to measuring the ${V}_{\text {th}}$ . The most recent standard JEP183A published in 2023 describes guidelines for ${V}_{\text {th}}$ measurement methods and preconditioning prior to ${V}_{\text {th}}$ testing in the N-channel SiC MOSFETs of vertical structure. The guidelines aim to reduce or eliminate the effects of ${V}_{\text {th}}$ hysteresis. However, the polarity of preconditioning voltage, preconditioning time, floating time, sweeping direction, and test duration all affect the test result of the threshold voltage. This article compares the threshold voltage instability of three commercially available SiC MOSFETs with various gate structures under different gate voltage sequences and provides in-depth analyses of the mechanisms behind the results. It also proposes response models between threshold voltage and three key time variables of gate voltage sequences. This article contributes to a deeper understanding of the impact of gate voltage sequences on threshold voltage instability of SiC MOSFETs. The results offer valuable insights for selecting suitable gate voltage sequences to improve the accuracy of threshold voltage measurement.