First Demonstration of 2D Semiconductor Vertical pFET with Symmetrical Source/Drain Transport of I on >100 μA/μm with Extremely High thermal Stability up to 550 ℃ by Scalable Direct Channel Growth

Vertical field-effect transistors (VFET) offer unique structural advantages for 3D integrated circuits. However, scalable implementations of two-dimensional (2D) semiconductor vertical transistors remain largely unexplored. In this work, we present the first demonstration of a self-aligned 2D semiconductor vertical pFET with a 20 nm physical gate length, enabled by direct source/drain seed-layer growth of the 2D channel for scalable integration. The device features a 2 nm-thick (tri-layer) p-type WSe2channel with excellent source/drain symmetry transport characteristics, exhibiting an on/off current ratio >107and an on-state current >100 μA/μm. The WSe2VFET also demonstrates thermal process tolerance at 550 °C and stable operation at 100 °C, attributed to the intrinsic single-crystalline quality of the WSe2channel and the high melting point of the tungsten (W) source/drain contacts. This work highlights the great potential of 2D semiconductors for thermal stability vertical transistors for future CFET logic and 4F2DRAM applications.