A 65pF-CL, −46dB-PSRR at 1MHz, Wide Supply Bulk-Biasing FVF-Based LDO Consuming 6.6 uA

A Flipped-Voltage-Follower (FVF) based LDO is implemented in 55nm CMOS for low-power audio applications. It includes an auxiliary path to provide a proper ac-only bias to the bulk of the pass pMOS transistor. This improves the Power Supply Rejection Ratio (PSRR) up to 17dB in the target frequency range, from 50kHz to 2MHz, at cost of 1.5μA additional current. Thus, a PSRR of −46dB at 1MHz is measured, despite the parasitic and coupling effects of the 55nm CMOS, only 6.6μA of LDO quiescent current and a limited 65pF on-chip load capacitor. Other measurement results include a 0.016mV/V line regulation, 0.036mV/mA load regulation and 250ns settling time under a full load step. The proposed bulk-biasing LDO is able to operate with a supply voltage in the 1.08V to 1.8V range, a maximum efficiency η>91% and 80mV minimum dropout.