Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe2 Semiconductor Devices

Palladium diselenide (PdSe2), as an emerging two-dimensional (2D) layered material, is gaining growing attention in nanoelectronics and optoelectronics due to its thickness-dependent band gap, high carrier mobility, and good air stability. However, its asymmetric pentagon structure is inclined to breed defects. Herein, the intrinsic Se vacancy-induced trap states and their influence on the hopping transport in PdSe2 are systematically investigated. We provide direct evidence that Se vacancies exist in the fresh PdSe2 samples, which results in the localized trapping states inside the band gap. For the few-layer PdSe2, at 77 K, the trap density (Dit) near the midgap is about 2.2 × 1013 cm–2 eV–1, whereas at 295 K, the Dit value increases to ∼7.1 × 1013 cm–2 eV–1. By comparison, the multilayer PdSe2 shows nonobvious temperature-dependent trap behaviors with almost unchanged Dit values of ∼8.1 × 1012 cm–2 eV–1 at midgap in the temperature range between 77 and 295 K. Thus, trap states in the few-layer PdSe2 are more vulnerable to temperature effect. Transport measurements demonstrated that both few-layer and multilayer PdSe2 field-effect transistor (FET) devices show n-type dominant ambipolar behaviors. The electron mobility in the multilayer PdSe2 FET is nearly 15-fold higher than that in the few-layer PdSe2 FET at 315 K, probably owing to the decreased effective mass and suppression of charge impurity scattering in the thicker channel material. However, both FET devices exhibit variable-range hopping over a temperature range from 77 to 240 K and thermally activated hopping at temperatures above 240 K. The hopping transport mechanism is strongly associated with the Se vacancy-induced localized states with poor screening and strong potential fluctuations. This study reveals the important role of structural defects in tailoring and improving the charge transport properties of PdSe2.