Repetitive ESD-Induced Electrical Degradation and Optimization for High-Voltage SOI-LIGBT as Output Device

In our work, the reliabilities and inner mechanisms of the high-voltage silicon-on-insulator lateral insulated gate bipolar transistors (SOI-LIGBTs) have been investigated comprehensively under the repetitive electrostatic discharge (ESD) stresses for better application on the high-voltage circuits. The worst repetitive ESD stress occurs when the SOI-LIGBT is getting snapback with the turn- ON of the parasitic transistor. In the worst transmission line pulse (TLP) stress I, the ON-state voltage ( ${V} _{\text {on}}$ ) and collector-to-emitter current density ( ${J} _{\text {ce}}$ ) are decreased as the stressing times. The decreased ${V} _{\text {on}}$ is attributed to the hot-hole injection at the gate plate edge, while the decreased ${J} _{\text {ce}}$ is attributed to the interface states generation at the gate plate edge and collector plate edge. The ${V} _{\text {on}}$ decrease is better for SOI-LIGBT, but the decreased ${J} _{\text {ce}}$ is the opposite. To restrain the ${J} _{\text {ce}}$ degradation, the P-top layer structure has been proposed and fabricated with the same mask of the P-body. Then, the measured ${J} _{\text {ce}}$ degradation shows effective improvement of the proposed device due to its remarkable weakness for the hot-carrier effects.