12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V<inf>MIN</inf> applications

The growing demand for battery powered mobile devices is a major driver for reducing power and continued area scaling in SOC chips. Continued scaling of the transistor and metal interconnection geometry is accompanied by increasing random V _t variation and increased wire routing resistance and capacitance variation in advanced technologies. Such variation degrades SRAM performance and its minimum operating voltage, which then seriously impact the battery life of mobile devices. FinFET technology provides a superior short-channel effect and less random dopant fluctuation. However, the quantized channel width and length force constrains on transistor sizing of high density SRAM bitcells. Figure 12.1.1(a) shows the layout of a high density 6T SRAM bit cell with a 0.027μm ² area in a leading edge 7nm FinFET technology. In order to achieve minimum area, all transistors (PU, PG, PD) in this bitcell have to be sized as single fin. Figure 12.1.1(b) shows a contention between the pull-up (PU) and the pass-gate (PG) transistors during a write operation. A stronger PU transistor results in better read stability, but the write margin is significantly degraded and results in elevation of minimum operation voltage for write operation. The negative bit-line (NBL) technique was proposed to improve write V _MIN in previous work [1-6]. In addition to transistor scaling, the geometric scaling of metal and via routing increases the back-end wire RC load, which also significantly degrades SRAM operation speed. In this work, we use a flying BL (FBL) and double WL (DWL) design to mitigate the RC wire load impact in order to improve SRAM array access performance.