放大器
CMOS芯片
无线电频率
静脉曲张
图像响应
谐波混频器
中频
射频功率放大器
噪声系数
电气工程
校准
W波段
电子工程
低噪声放大器
本振子
物理
电容
工程类
电极
量子力学
作者
Yongho Lee,Soyeon Kim,Hyunchol Shin
出处
期刊:Sensors
[Multidisciplinary Digital Publishing Institute]
日期:2022-10-27
卷期号:22 (21): 8246-8246
被引量:4
摘要
A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer's LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, -35.2 dBm input-referred 1 dB compression power, and 4.8-7.1 dB noise figure across 22.5-26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0-1.5 dB to 0.02-0.19 dB, and from 10.8-23.8 to 1.1-3.2 degrees, respectively.
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