Design of High-Bandwidth, High-DC Gain Single-Stage Amplifier for High-Speed ADCs

Many modern, high-speed, high-performance applications require analog-to-digital converters (ADCs) that operate in high frequency. This paper presents the design and simulation of a high gain bandwidth (GBW), high gain, high-power-bandwidth efficiency fully differential single-stage operational amplifier (Opamp) implemented in 65nm CMOS technology. The Opamp was designed suitable for high-speed pipeline ADC building blocks such as the sample-and-hold (S/H) stage, a multiplying digital-to-analog converter (MDAC). The proposed topology uses a single-stage folded-cascode with Nauta transconductor assisted gain boosting to simultaneously achieve independent DC gain and GBW boosting. The PVT variations from the inverter-based Nauta transconductor are compensated using a process compensated biasing architecture to stabilize the regulated cascode loop gain and GBW under different process corners. The simulated Opamp achieves a DC gain of 75 dB, unity-gain bandwidth of 1.5 GHz under 4pF load, and a phase margin of SO degrees. The settling time is 5.5 ns, and the Opamp consumes power of 6 mW with a supply voltage of 1.2 V.