37.9 A 14Gb/s/pin 0.163pJ/b DQ Receiver for HBM with Baud-Rate Phase Tracking Loop Supporting Background Offset Calibration

This paper presents a compact 14Gb/s/pin HBM DQ receiver that continuously tracks sampling phase and detector offset in live data, using a baud-rate phase tracking loop with a background-calibrated time-window phase detector. Rise/fall edge-triggered decision logic decouples phase error from detector offset, keeping the sampling-clock lock point of the DCDL fixed under drift and thereby eliminating the need for retraining. A 28nm prototype achieves 0.163pJ/b energy efficiency in 0.00547mm² at <10⁻¹² BER with a 0.295UI sampling margin. High-frequency jitter tolerance reaches 0.188UI at 14Gb/s.