Delay and Offset Compensated Relaxation Oscillator Core with Replica Integrator

This work presents a novel relaxation oscillator core architecture using a replica integrator and a chopped comparator, suitable for advanced technology nodes. The oscillator core receives two reference voltages and three reference currents, based on which the output clock is generated having the frequency invariant to delay and offset of the comparators. The oscillator core prototype is designed in 110 nm technology, having an area of 0.045 mm ² and typically consuming 33 µA at 2 MHz. The frequency variation is ±0.5% in the temperature range from −40 to 125°C and ±0.33% in the power supply range from 1.08 to 1.32 V. The core starts up after a single half-cycle.