Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

Abstract This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO 2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO 2 ) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents I ON /I OFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10 −17 A μ m −1 ) is provided by the proposed device structure, improved ratio of I ON /I OFF (10 11 ), and lowered subthreshold swing required for future era.