A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction

This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is proposed for the flash sub-ADC-based pipeline ADC to reduce the aperture error, and expand the ADC input frequency up to 490 MHz under 200-Ms/s sampling rate. To further improve the accuracy and reduce power, the sampling capacitor splitting and comparator interpolation techniques are used in the first stage. The proposed ADC has been designed and fabricated in a 180-nm CMOS technology with an area of 2.43 mm ² including ADC core, the biasing, and the calibration circuit. The measured signal to noise and distortion ratio (SNDR) is 70.6 and 65.6 dB for 30- and 385-MHz inputs, respectively. The SNDR remains 63.1 dB for 490-MHz input. The ADC core consumes 112-mW power under 1.8-V supply. The measured effective resolution bandwidth (ERBW) is about 250 MHz, and the Walden figure of merit (FoM) defined at the ERBW is 116 fJ/conversion-step.