Optimization of Specific On-Resistance for Superjunction With Insulating Pillar Including Temperature Dependence

Unified temperature-dependent models are developed to optimize R_sp for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement R_sp compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best R_sp, especially with high BV and narrow half cell width b, and large drain-to-source voltage (V_DS), due to better suppression of JFET effect. For BV = 1250 V and b = 0.6 μm, theoretical optimization predicts a largest reduction up to 20.5% in R_sp with V_DS= 5 V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.