Device overlay root cause process detection using patterned wafer geometry information

On-product overlay (OPO) is a critical inline process control parameter in semiconductor manufacturing. One of the main factors that induce the overlay error is non-lithography processes like etching, deposition and cleaning. The overlay margin is getting tighter as the device technology advances and detecting the root cause of process-induced overlay error is a main problem to improving the OPO. However, it is not an easy problem to solve due to the lack of inline monitoring data on non-lithography processes. Even if we evaluate inline monitoring data, it is too sparse to do in-depth analysis compared to abundant lithographic overlay data. Instead, we can make use of data from the PWG patterned wafer geometry metrology system, which can measure high-density data with high throughput. In this paper, we introduce a comprehensive method of detecting the root cause of the process-induced overlay errors based on inline PWG data. Our target device is a 3D NAND product with process-induced overlay errors due to wafer geometry. We start our analysis by tracing PWG GEN3 data for the same wafer in a wide process step range. We compare the GEN3 signature to an overlay error signature of a target lithography layer to filter out suspicious processes. From the suspicious processes, we derived optimized KPIs that discriminate between good and bad wafers in terms of process-induced overlay errors, which are then used as a monitoring metric. With the optimized KPIs, we discern which process is the root cause of process-induced overlay errors to help drive corrective actions and improve OPO on the target device. Finally, we propose a comprehensive framework that is not limited to PWG data but applies to other available inline data such as alignment, ADI and AEI overlay and NZO.