A Low‐Power Triple‐Node‐Upset Recovery Hardened Latch Based on Triple Modular Redundancy

ABSTRACT With the advancement of CMOS technology, transistor sizes have been continuously shrinking, making electronic devices more susceptible to radiation effects in radiation environments. In order to address this challenge, various radiation‐hardened latch designs have been proposed. However, these designs incur excessively high power consumption in the latches due to the use of a large number of redundant units and the absence of clock gating techniques in some structures. Therefore, this paper proposes a low‐power triple‐node‐upset recovery hardened latch (LPHL). Compared to other triple‐node‐upset self‐recovering latches, the proposed LPHL achieves an average reduction of 44.23% in power consumption and 14.85% in delay overhead. Furthermore, the robustness of the LPHL latch is validated through PVT (process, voltage, temperature) and Monte Carlo simulations, demonstrating its excellent stability under variations in process corners, supply voltage, and temperature.