High-performance Vertical Gate-All-Around Oxide Semiconductor Transistors with 6 nm ALD IGZO Channel and Scaled Contact CD down to 28 nm

Vertical gate-all-around (GAA) indium-gallium-zinc-oxide (IGZO) FETs are demonstrated on an 8-inch platform with a thin IGZO channel of 6 nm and a short gate length of 48 nm. The device exhibits a high on-state current$(\mathrm{I}_{\text{ON}})$of$111.4\ \mu\mathrm{A}/\mu \mathrm{m}$@$\mathrm{V}_{\text{DS}}=1.5\ \mathrm{V},\ \mathrm{V}_{\text{GS}}=2\ \mathrm{V}$with scaled source/drain (SD) contact CD of 40 nm, a positive threshold voltage (VTH) of 0.13 V, a low SS of 75 mV/dec, and a small drain induced barrier lowering (DIBL) of 20.9 mV/V. Further scaling SD CD to 28 nm leads to a slightly drop of$\mathrm{I}_{\text{ON}}$to$95.5\ \mu\mathrm{A}/\mu \mathrm{m}$. The stability and BEOL compatibility of devices are also evaluated. Excellent bias temperature stability (BTS) is obtained with optimized gate stack, showing a small$\mathrm{V}_{\text{TH}}$shift of$\pm 3\ \text{mV}$after stressing 1k seconds under$\mathrm{V}_{\text{GS}}=\pm 2\ \mathrm{V}$. The device characteristics are well maintained with small$\mathrm{V}_{\text{TH}}$shift of 28 mV after annealing in$\mathrm{N}_{2}$at 400°C for 1 hr, indicating good stability with BEOL compatible thermal budget. Our results prove that IGZO is a promising channel material for high-density scaled BEOL transistor applications.