Parasitic Model to Describe Breakdown in Stacked-FET SOI Switches

A simple passive capacitance model has been optimized to predict breakdown in a stacked SOI FET. Specifically, as the number of FETs in a switch increases, an equivalent increase in breakdown is not seen in hardware; instead, the breakdown performance saturates as the number of stacks in the FET increases. This phenomenon is not predicted by the FET foundry model. This work is focused on FETs for RF switches in flip chip topologies. As a result of this work, the different components that contribute to off-state capacitances were also described which is important for model development and accuracy.