Hardware accelerator using Gabor filters for image recognition applications

This paper presents the design of a new hardware accelerator, filtering the input data using Gabor functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources if compared to other state-of-the-art implementations. This is done exploiting the separability of Gabor filters along certain orientations and through a reorganization of the arithmetic units and the memory structures, achieved thanks to the absence of frame buffers to store the entire input image and partially processed data. All the above reported features allow the design to obtain real-time performances. The design has been targeted to a Xilinx Virtex 7 ASIC board and to CMOS 90nm std_cells, obtaining a minimum operating clock period of 5.8 ns for the FPGA implementation and of 2.9 ns for the std_cell one. The above reported results allow to process 83 and 168 1920×1080 pixels (Full-HD) frame-per-second, respectively.