积分器
逐次逼近ADC
无杂散动态范围
比较器
过采样
电子工程
线性
带宽(计算)
采样(信号处理)
计算机科学
功勋
传递函数
积分ADC
CMOS芯片
物理
电容器
电气工程
工程类
探测器
电压
电信
光学
Ćuk转换器
作者
Hanyue Li,Yu-Ting Shen,Eugenio Cantatore,Pieter Harpe
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-01-01
卷期号:58 (4): 939-948
标识
DOI:10.1109/jssc.2022.3227678
摘要
This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming $13.5~\mu \text{W}$ , leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.
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