A Low-Noise CMOS Image Sensor With Digital Correlated Multiple Sampling

This paper presents a low noise CMOS image sensor using conventional 3T active pixel with Nwell/Psub diode as photo detector. Both fixed pattern noise (FPN) and temporal noise are suppressed by the proposed digital correlated multiple sampling (DCMS) technology. FPN and temporal noise from pixel, buffer circuit, and column-parallel ADC are analyzed in detail, and the total noise with DCMS is derived. General expression of 1/f noise with correlated multiple sampling is given, illustrating impact of delay time in DCMS. Output noise of image sensor, frame rate, power, and area are affected by order and oversampling ratio of sigma-delta ADC, which are discussed for practical design. A prototype CMOS image sensor with 800×600 pixel array and second-order incremental sigma-delta ADCs is implemented with the 0.35-μm standard CMOS process. Measurement results of the implemented image sensor show a column FPN of 0.009%, an input referred noise of 3.5 e _rms ^- , and a dynamic range of 84 dB with oversampling ratio of 255. This indicates that image sensor with low noise can be achieved by DCMS without the CIS process and column amplification.