FPGA Implementation of Convolutional Neural Networks Based on Resource Sharing Techniques

Convolutional neural networks(CNNs) are now widely used in image processing.For large-scale CNNs,computationally intensive convolutional layers are one of the main challenges in implementing CNNs in FPGAs.In view of the limited resources of FPGA,this paper proposes a general line buffer structure and DSP resource sharing technology for the implementation of convolutional circuits,aiming to improve the parallelism of convolutional operations and increase the resource utilization,so as to maximize the performance of the accelerator.We deployed the CNN model on a Xilinx ZYNQ xc7z035 FPGA using a modified circuit, achieving 0.48GOP/S performance at 200Mhz system clock frequency with low power consumption.