A Novel Hardware Structure Design for DSP Memory Control

Basing on the demand of digital signal algorithms,the memory access operation of them is analyzed and then a novel architecture memory control unit is proposed in this paper.When the memory is accessed,the unit can execute some micro-operation which is optimized for memory access such as autoincrement and autodecrement in parallel and also support circular queue.In the end,a hardware implementation using CSA architecture is proposed.The whole memory control unit can achieve all the functions mentioned above through the method,and achieve about 45% speed improvement in the cost of about 10% extra area penalty.