Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Abstract Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO 2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm 2 V –1 s –1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm –1 ) and peak transconductance (0.98 mS μm –1 ). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm 2 , representing the fastest and the most compact M3D ICs to date. image