High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism

In this paper, a novel encoding method is proposed to reduce the energy consumption of the Booth multiplier. The method can convert non-zero encoding to zero encoding of the radix-4 Booth algorithm, which increases the number of zero encodings and thus reduces the number of multiplication operations. The multiplier with zero encoding skipping mechanism is proposed, which is an improvement of the radix-4 Booth serial multiplier. It detects zero encoding of the Booth encoding, then skips the partial product and addition calculation of zero encoding. In this way, the total computation time is reduced and the energy consumption is also significantly decreased. The multiplier was synthesized using a standard CMOS 40nm process with energies of 0.41 pJ and l.56pJ based on the typical 16-bit and 32-bit width. Compared with other multipliers, the results implemented show a significant energy efficiency advantage over existing multiplier designs.