Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO _x interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10 ^-6 A/cm ² (10 ^-8 A/cm ² ) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (>; 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.