The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR

In this work, we focus on the Power Supply Rejection and Common Mode Rejection performance of inverter based ring oscillators intended for use in VCO ADCs. We show that they are closely related to the circuit's mismatch behavior of which we perform a systematic analysis. To this end, we construct a theoretical mismatch model for these ring oscillators, based on Pelgrom's mismatch model. In addition, we generalize this model to include the mismatch in a generic tuning circuit. In this broad analysis, we show that, next to the obvious transistor size dependence, the mismatch is inversely proportional to the number of stages and hence, in theory, can always be suppressed up to the desired level in a VCO ADC, provided that the tune circuit is sized adequately. Furthermore, we demonstrate that the mismatch is dependent on the biasing of the ring, which becomes even more apparent when taking into account the influence of a tuning circuit. More specifically, strong inversion is almost always better than weak inversion, and current control is preferred over voltage control. Finally, we perform extensive Monte Carlo simulations, with a commercially available 65nm CMOS process, which match our analytical predictions nearly perfectly.