NLTF based BIST circuit for DRAM testing

DRAM testing is of major importance in systems reliability. Effective fault models, like the Neighborhood Leakage and Transition Fault (NLTF) model, can be exploited for DRAM testing. An efficient NLTF-based Built-In Self Test (BIST) circuit, for the acceleration and simplification of DRAM testing procedures, is presented in this work.