Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology

In this paper, a new structure is presented to realize a high-speed high-precision two-stage comparator. Positive feedback is employed in the first stage of the offered comparator to reduce the delay time. Furthermore, by using an NMOS transistor between the differential output nodes of each stage in the reset mode, the comparison speed is enhanced. Moreover, the second stage of the offered comparator is activated with a preset delay to improve the speed and accuracy of the comparison. Furthermore, by using intermediate transistors between the two stages of the comparator, the delay time and the comparison accuracy is also improved. The delay and offset equations of this comparator are also extracted, and the main contributors in decreasing them are recognized. The proposed circuit is simulated in 65 nm CMOS technology. The post-layout results show that the total delay and standard deviation of input-referred offset voltage of this comparator are 40 ps and 5.69 mV, respectively. This comparator consumes 395.3 μW @ 6 GHz and 38 μW @ 1 GHz with a single supply voltage of 1.2 V. Moreover, the proposed comparator occupies the area of 115.92 μm2 (12.6 μm× 9.2 μm).