A Low-Power FR3 Passive-Mixer-First Receiver Employing a Class-${\text{F}}^{{-}1}$ Quadrature Oscillator and Modal Front End

This work presents a low-power (LP), high-dynamic-range passive-mixer-first receiver (PMFRX) targeting narrowband operation, 12.3–14.5 GHz, within the proposed 6G FR3 band (7.125–24.25 GHz). The receiver architecture achieves enhanced performance at reduced power by directly driving the mixers with harmonically enhanced (HE) local oscillator (LO) waveforms generated on-chip using a quadrature Class-${\text{F}}^{{-}1}$oscillator. To further improve robustness and efficiency, a passive front-end (FE) network is introduced between the$I$and$Q$sub-mixers to suppress overlap conduction losses across a wide range of mixer bias conditions. This feature allows the receiver’s LO power consumption to back off without severely degrading sensitivity, primarily trading off against interference tolerance. The chip was fabricated in a 16-nm FinFET process. In near-maximum power mode, the prototype demonstrates a noise figure (NF) of 4.2 dB, an out-of-band third-order input intercept point (OOB-IIP3) of 7.3 dBm, and a blocker 1-dB compression point (B1dB) of −5 dBm while consuming 11.5 mW. When power is backed off to 5.9 mW, it maintains 5.4-dB NF, 3.9-dBm OOB-IIP3, and −9.7-dBm B1dB, highlighting the effectiveness of the proposed HE LO generation and FE network in enabling scalable, power-adaptive PMFRX architectures for future FR3 applications. The prototype occupies 0.28 mm2.