A 20mW 61dB SNDR (60MHz BW) 1b 3<sup>rd</sup>-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS

Continuous-Time ΔΣ Modulators are a popular architecture choice for ADCs in deep-submicron processes [1-4]. The maximum sampling rate is set by Excess Loop Delay (ELD) considerations. ELD comprises the comparator latency, feedback DAC delay (DEM delay etc.) and any additional delay due to parasitics. For a wideband 1b modulator clocking at high speeds (multi-GHz), the key challenge is modulator stability due to large ELD set by comparator speed limitations and integrator parasitic poles. This paper describes circuit techniques to minimize ELD and a compensation scheme that ensures modulator stability given a 1-clock-period ELD. These techniques have enabled the design of a 3 ^rd -order 1b modulator clocked at 6GHz in 45nm CMOS.