Synergistic Optimization of Charge Transport Layers for High-Efficiency Pb-Free CsSnI3 Perovskite Solar Cells

作者
Yunxiang Zhang,Yuxin Zhang,Yuxin Zhang,Zihan Tao,Xinru Wang,Keshun Nie,Qinfang Zhang
出处
期刊:Semiconductors [Pleiades Publishing]
卷期号:60 (8): 890-906 被引量:1
标识
DOI:10.1134/s1063782626601317
摘要

Abstract Lead-free inorganic tin halide perovskite CsSnI3 holds great promise for environmentally friendly photovoltaics, however it suffers from inefficient charge transport and interfacial recombination. This work presents a comprehensive numerical study using SCAPS-1D to synergistically optimize the electron transport layer (ETL, TiO2) and hole transport layer (HTL, Spiro-OMeTAD) in CsSnI3-based perovskite solar cells (PSCs). An optimal thickness of ~50 nm and a carrier concentration of ~1 × 1018 cm–3 for TiO2 ETL yield the device performance of 18.13%, balancing the efficient electron extraction with minimized recombination. Device performance is more sensitive to the carrier concentration of the HTL than to that of the ETL. The CsSnI3 layer performance is governed by the balance between the light absorption and recombination. The efficiency of solar cells increases significantly with carrier concentrations, peaking at 26.75% for doping levels between 2 × 1018 to 1 × 1019 cm–3. This peak performance coincides with a maximal FF of 86.90% and an improved VOC, the latter driven by a stronger built-in electric field (IEF) enhancing the charge separation. These conversion efficiencies are theoretical upper limits (experimental devices currently achieve 14–17%), so the primary value of this work lies in the relative trends and optimal parameter ranges rather than the absolute numbers. In conclusion, this simulation study elucidates that synergistic optimization of ETL/HTL properties, focusing on thickness, carrier concentration, and defect minimization, is an important factor for improving device performance of lead-free tin-based perovskite solar cells, offering a potential theoretical reference for the experimental device engineering.

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