Forming a more robust sidewall spacer with lower k (dielectric constant) value

Device scaling leads to tough challenges not only in patterning, but also in device performance due to scaled contact area, smaller stressors, and increased parasites capacitance. There is immediate need to implement low k spacers. Low-k materials, however turn out to be weak, especially after going through subsequent integration, such as cleans and etching. Here we report issues with integrating low-k spacers materials in the state-of-the-art CMOS technologies and propose one method to solve these issues.