Fourier-filtering-based defect inspection of logic circuit patterned wafer achieving ~50 nm precision

Advancements in the wafer manufacturing industry have been challenged by the need for high-sensitivity inspection of defects far beyond the optical diffraction limit. The conventional crossed Nicols configurations (CNC) utilizing the offaxis and polarized illumination has markedly enhanced the detectability for nanoscale defects in the line and space (L/S) arrays. However, this approach fails for logic circuit patterns, where polarization dependence is significantly weakened, leading to a drastic drop in signal to noise ratio (SNR) and rendering defect detection ineffective. Here, we established a simulation framework to model diffraction propagation from wafer near-fields to far-field images, enabling quantitative SNR comparison and propose a dedicated inspection scheme for ~50nm defect in complex logic circuit patterns based on the spatial Fourier filtering method. The results demonstrate the modeling framework’ capability for the qualitative analysis, with the Fourier filtering significantly enhancing SNR for ~50 nm defects in logic patterns (making obscured defects visible. This cost-effective method, requiring only a simple Fourier spatial filter at the microscope objective pupil plane, offers a promising direction for advancing high-precision defect inspection in advanced semiconductor manufacturing.