抵抗
多重图案
材料科学
平版印刷术
光刻胶
薄脆饼
浸没式光刻
进程窗口
临界尺寸
光电子学
光刻
光学
堆栈(抽象数据类型)
表面光洁度
纳米技术
图层(电子)
计算机科学
复合材料
物理
程序设计语言
作者
Katsumi Ohmori,Naoto Motoike,Hidetami Yaegashi,Kenichi Oyama
摘要
Double patterning techniques (DPT) with 193nm immersion lithography are being thought to be one of the most promising candidates for the 22nm node and beyond. Especially, self-aligned spacer double patterning (SADP) has already been established as pitch doubling process and adapted in high volume manufacturing of NAND flash memory device. Moreover, ultra fine resolution can be obtained to repeat the SADP step twice as pitch quadrupling. Simple cost effective SADP scheme which is resist core SADP process has already been demonstrated to obtain not only simple line and space patterning also trench and 2D patterning as well by Tokyo Electron LTD.[1, 2, 3] In this process, a SiO2 spacer film is being directly formed on a tri-layer resist stack. This pattern is then transferred onto an underlying spin-on carbon (SOC) film and the final pattern is resolved on the TEOS film. Roughness and verticalness of resist pattern could affect the quality of SiO2 spacer film deposition and it could determine the CD uniformity of final pattern. Therefore, it's been thought that low line-width roughness (LWR) resist pattern and vertical resist profile make a better CD contribution and uniformity on final pattern. Experimental results on SADP process will be shown and then it'll be discussed that specially designed resist materials which indicates small LWR and vertical profile could have a potential to improve CD uniformity after pitch splitting SADP process.
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