Design and Optimization of 60v LDMOS in 0.18mm BCD Platform with Enhanced Performance Via STI Engineering

This work investigates the design and optimization of a 60V STI LDMOS transistor in a 0.18μm BCD process. The study uses TCAD simulations and experimental validation to optimize structural parameters, such as field-plate length and drift-region implantation conditions, to improve breakdown voltage (BV) and on-resistance (Ron,sp). A new asymmetric step-type STI (SSTI) structure is proposed to enhance BV while mitigating the BV-Ron,sp trade-off. The simulation results demonstrate a significant improvement in both BV and figure of merit (FOM), showing that the SSTI design improves the overall performance of STI LDMOS devices on BCD platforms.